Asynchronous processors do not use a clock to implement the operating of different operations. One of those operations includes the execution of the instructions of the processor.
The potential advantages of asynchronous and in particular quasi-delay-insensitive implementations of data processors have been described in the prior art. See for instance U.S. Pat. No. 5,752,070 to Martin and Barnes, and other U.S. patent applications by the present inventor.
This application relates more specifically to the case when the processor is pipelined. Pipelining is a standard technique in modern processor architecture and is well described in the literature. For instance, the standard computer architecture text by Hennessy and Paterson describes pipelining in great detail. Pipelining is an implementation technique whereby multiple instructions are simultaneously overlapped in execution. Today, pipelining is the key implementation technique to make CPUs.
A pipeline is like an assembly line: Each step in the pipeline completes a part of the instructions. As in a car assembly line, the work to be done is an instruction is broken down into small pieces, each of which takes a fraction of the time needed to complete the entire instruction. Each of these steps is called a pipeline stage.
In an asynchronous process, a pipeline stage communicates with other stages by exchanging messages. Typically, a stage receives data from a plurality of stages; it then processes the data, and sends the results to a plurality of stages. Each stage proceeds at its own speed. The communication between stages (send and relaying) synchronizes the activities of the different stages.
In a traditional, clocked pipelined processor, the number of instructions in execution in the pipeline is fixed in normal operation. In an asynchronous pipeline, because each stage proceeds at its own speed, the number of instructions in execution is variable. This difference is very important when it comes to dealing with "exceptions".
An exception, also called "interrupt", is a hardware and/or software mechanism that makes it possible to interrupt the normal execution of instructions when an exceptional event occurs that requires immediate processing. Such an event is usually an arithmetic error, or a real-time event, or an I/O. Modern exception mechanisms are used for other purposes like training instruction execution, operating system calls, page fault, memory and protection isolation, undefined instructions, protection isolations, hardware malfunction, power failure, etc.
The handling of an exception has a number of steps. (1) the exception is detected, (2) the necessary information relative to the exception is saved into some registers, in particular the program counter value of the instruction that caused the exception, and the nature of the exception, and (3) the program counter is assigned the address of the first instruction of an exception handling routine.
In the case where the processor is pipelined, several instructions may already be in execution when the exception occurs. In that case, all instructions already in execution in the pipeline have to be canceled. The exception mechanism is said to implement precise exceptions when the state of the execution saved for the exception handling routine is the same as the state of the processor before execution of the instruction that caused the exception. As a result, after the exception handler has finished, the execution of the program can be restarted from the point where the exception occurred, without affecting the program behavior.
In a clocked pipeline, all stages are controlled by the same global time reference. When an exception occurs, it is relatively straightforward to take a "snapshot" of the state of the pipeline. In particular, the number of instructions in the pipeline is fixed, and it is therefore straightforward to cancel all instructions in the pipeline.
In an asynchronous pipeline, there is no global clock. The number of instructions in the pipeline is variable. Hence, implementing precise exceptions is more difficult.